A Critical Analysis on FPGA–CGRA Co-Design for Energy-Efficient Edge AI Systems
DOI:
https://doi.org/10.54097/7mse0b90Keywords:
FPGA, CGRA, Co-Design, Energy-efficient.Abstract
With the advancement of artificial intelligence (AI) in Internet of Things (IoT) devices, drones, wearables, and autonomous robots, the need for real-time processing edge AI processors has grown significantly. Architectures like field-programmable gate arrays (FPGAs) and coarse-grained reconfigurable architectures (CGRAs) have advancements in a particular field, but the stringent requirements of latency, power, and performance may not be met, respectively. Existing studies typically analyze FPGA-CGRA in isolation, leaving a limited understanding of the methodology and functionality of the hybrid architecture. Therefore, this review examines how hybrid FPGA-CGRA computing addresses problems like power efficiency and flexibility and found that it could achieve 1.93x higher peak performance and 48.5% area saving compared to a singular architecture alone. However, its limitations also need to be considered, such as performance overlay and high resource consumption. This research provides important insights for designing next-generation edge computing accelerators that balance flexibility, efficiency, and real-time processing needs.
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